Federal Agency of Railway Transport

Far Eastern State University of Communications

Department of Telecommunications

Course project

By discipline: "Microprocessor-based information control systems"

On the topic: "Microcontrollers family AVR company Atmel"

khabarovsk

Introduction

In the classical microprocessor system, a separate processor chip, separate memory chips, and separate input / output ports are used. The rapid development of microprocessor technology requires a greater and greater degree of chip integration.

That is why microcircuits were developed that combine all elements of a microprocessor system at once. Such microprocessors are called microcontrollers. In Soviet times, such chips were called “single-chip microcomputers”.

For single-chip microcontrollers, the concept of "central processor" is usually not used. Since the processor is still a separate device. The functions of the processor in the microcontroller replaces the arithmetic logic unit (ALU).

In addition to the ALU, the microcontroller contains in its composition:

♦ clock generator;

♦ data memory;

♦ program memory;

♦ I / O ports.

All these elements are interconnected by internal data and address buses. The microcontroller communicates with the outside world using input-output ports. Any microcontroller always has one or more ports. In addition, modern microcontrollers always have a built-in interrupt system, as well as built-in programmable timers, comparators, digital-to-analog converters, and more.

If we are not talking about a large computer, but about a portable control device, then it uses microcontrollers. Of course, any real scheme rarely does without simple logic chips, flip-flops, counters, and the like. But the basis is always the microcontroller. Pure microprocessors are currently used only in personal computers.

1. Atmel ATtiny2313 / V microcontroller

1.1 Structure, key features and capabilities

The ATtiny 2313 microcircuit is an eight-bit microcontroller with an internal programmable flash memory of 2 KB in size.

General information:

♦ uses AVRRISC architecture;

♦ AVR is a high speed and special low-power RISC architecture;

♦ 120 powerful instructions, most of which are executed in one machine cycle;

♦ 32 eight-bit general purpose registers;

♦ completely static organization (the minimum frequency can be equal to 0);

♦ up to 20 million operations per second (MIPS / Sec) with a clock frequency of 20 MHz.

Saving programs and data with power off:

♦ 2 Kbytes of built-in programmable flash memory, up to 10,000 write / erase cycles;

♦ 128 bytes of built-in programmable non-volatile data memory (EEPROM);

♦ up to 10,000 write / erase cycles;

♦ 128 bytes of internal RAM (SRAM);

♦ programmable protection bits for reading and writing program memory and EEPROM.

Peripherals:

♦ one 8-bit timer / counter with programmable determinant and coincidence mode;

♦ one 16-bit timer / counter with programmable determinant, coincidence mode, and capture mode;

♦ four channels PWM (PWM);

♦ built-in analog comparator;

♦ programmable watchdog timer and built-in clock generator;

♦ Universal Serial Interface (USI);

♦ full duplex USART.

Features of the microcontroller:

♦ debug WIRE special input for controlling the integrated debugging system;

♦ internal programmable serial interface SPI;

♦ support for both external and internal sources of interruptions;

♦ three low consumption modes (Idle, Power-down and Standby);

♦ Built-in hardware reset when power on;

♦ internal tunable clock generator;

♦ I / O circuit and case;

♦ 18 programmable I / O lines;

♦ three types of enclosures;

PDIP– 20 contacts;

SOIC - 20 contacts;

QFN / MLF - 20 contact pads.

Power supply:

♦ 1.8 - 5.5 V (for ATtiny2313V);

♦ 2.7 - 5.5 V (for ATtiny2313).

The frequency range of the ATtiny2313V clock generator:

♦ 0-4 MHz at a voltage of 1.8-5.5 V;

♦ 0–10 MHz at a voltage of 2.7-5.5 V.

The frequency range of the ATtiny2313 clock generator:

♦ 0-10MHz with a voltage of 2.7-5.5 V;

♦ 0–20 MHz at a voltage of 4.5-5.5 V.

Current consumption in active mode:

♦ 1 MHz, 1.8 V: 230 μA;

♦ 32 kHz, 1.8 V: 20 μA (with internal generator).

Current consumption in low consumption mode:

♦ not more than 0.1 µA at a voltage of 1.8 V.

Microcontroller block diagram

The pin assignment of the ATtiny2313 chip is shown in fig. 1. The block diagram of the ATtiny2313 microcontroller is shown in fig. 2

The AVR core has a large set of instructions for working with 32 general-purpose registers. All 32 registers are directly connected with an arithmetic logic unit (ALU), which allows you to execute a command for two different registers in one clock of the system generator. This architecture allowed to achieve a performance ten times greater than that of traditional microcontrollers, built on CISC-technology.

Fig. 1 - Pin assignments for the ATtiny2313 chip

1.2 Features of the ATtiny2313 chip

The ATtiny2313 chip has the following features:

♦ 2 Kbytes of system programmable Flash-memory programs;

♦ 128 bytes EEPROM;

♦ 128 bytes of SRAM (RAM);

♦ 18 I / O lines;

♦ 32 working registers;

♦ single-wire interface for on-chip debugging;

♦ two multifunctional timers / counters with a match function;

♦ support for external and internal interrupts;

♦ serial programmable USART port;

Fig. 2 - Block diagram of the ATtiny2313 microcontroller

♦ universal serial interface with the detector of the beginning of transfer;

♦ programmable watchdog timer with internal generator;

♦ three programmable power saving modes.

In Idle mode, the CPU is suspended, the rest of the systems continue to work. Exit from this mode is possible both by an external interrupt and by an internal one. For example, when the timer overflows.

In PowerDown mode, the contents of the registers are saved, but the operation of the internal generator is suspended and all other functions of the chip are turned off. Exit mode is possible by an external interrupt or after a system reset. This solution allows you to combine fast start with low power consumption.

The microcircuit is manufactured using Atmel's unique high-frequency technology. The internal flash memory of programs can be reprogrammed using the ISP interface without removing the microcontroller from the board. Combining an 8-bit RISC processor in-system flash memory on a single chip makes the ATtiny2313 chip a powerful tool that provides very flexible and inexpensive solutions to many application management tasks.

In my course project will be described some of the microcontroller.

2. The central core of the processor

The main function of the central processor core is the control of the program execution process. To do this, the CPU must have direct access to the memory, must be able to perform all types of calculations and perform interrupt requests.

Consider the general issues of the AVR architecture.

2.1 Summary of architecture

To speed up the work as much as possible and to enable parallel execution of several operations, AVR microcontrollers use the Havard architecture (Fig. 3).

Fig. 3 - Block diagram of the AVR architecture

This architecture provides a separate memory and a separate address bus for both the program and the data.

Each team of five programs are executed in one machine cycle using multilevel pipelining. At the moment when the next command is executed, the next command is read from the program memory. This concept allows you to perform one command at a time in a system clock. The program memory segment is physically a built-in reprogrammable flash memory.

The file of quick access registers contains 32 eight-bit general-purpose registers, access to which is carried out in one clock of the system generator. This allows the arithmetic logic unit (OLU) to perform most of its operations in one clock cycle.

A typical ALU operation is performed as follows: two operands are read from a register file, an operation is performed. The result of the save is again in the register file. All these three actions are performed in one cycle of the clock generator.

Six of these 32 registrars can be used as three 16-bit indirect addressing registers. These dual registers can be used to address data in the RAM address space. Such an organization makes it possible to programmatically calculate the address.

One of these register-pointers can also be used as a pointer to the address of the data stored in the program memory (Flash-memory). These additional composite 16-bit registers are referred to as X, Y, and Z.

The ALU supports arithmetic and logical operations between two registrars or between a constant and a registrar. In the ALU, operations can also be performed with individual registrars. After each arithmetic operation, the status register is updated to reflect information about its result.

The sequence of the program can be changed by the conditional and unconditional branch commands, as well as the subroutine call command, which uses direct addressing.

Most AVR instructions are one 16-bit word. Each memory address of the program contains a 16-bit instruction or half a 32-bit instruction.

When executing an interrupt or routine routine, the current value of the program counter (PC) is stored on the stack.

The stack is actually located in the same address space with SRAM (RAM) data memory and, therefore, the stack size is limited only by the size of the SRAM and by what part of the SRAM the rest of the program uses.

The user program must necessarily initialize the stack pointer (SP) immediately after a reset (before a subroutine is executed or an interrupt is triggered). The stack pointer (SP) has its specific address in I / O register space. Data in RAM (SRAM) can be accessed using memory of various addressing methods supported by the AVR architecture.

The address space of all kinds of memory in the AVR architecture is regular linear. The flexible interrupt module has a number of control registrars in the address space of I / O registers and an additional flag for global resolution of interrupts in the status register.

Each interrupt type has its own separate vector in the interrupt vector table. Interrupts take precedence according to their position in the interrupt vector table. The lower the interrupt vector address, the higher the priority.

The I / O register space contains 64 addresses for peripheral control registers, processor control registers, and other input / output functions. Any I / O register can be accessed directly by its number or as a data memory cell. In the address space of the data memory, I / O registers are located immediately after the general-purpose register file (0x20 - 0x5F).

2.2 ALU - arithmetic logic unit

The highly efficient ALU works in direct communication with all 32 general-purpose registers. In one cycle of the clock generator, an arithmetic operation is performed between the two RON or between the RON and the directly specified constant. All ALU operations are divided into three main categories:

♦ arithmetic;

♦ logical;

♦ operations with discharges.

The peculiarity of the architecture is that when performing arithmetic operations, all operands can be considered both unsigned and signed numbers.

Status Register

The status register contains information on the results of the execution of the last arithmetic or logical command. This information can be used to change the program execution process in conditional jump instructions and other conditional statements.

When calling the interrupt handling procedure, the status register is not automatically saved. The programmer must necessarily provide in the procedure for processing interrupts commands that will save the contents of this register at the beginning and restore it at the end. It is necessary to consider that the status register cannot be directly placed in the stack memory. First you have to save one of the general registers in the stack, then put the contents of the status register into the released register, and then from this intermediate register to move the information to the stack.

General purpose registers file

The register file is optimized for a set of AVRRISC instructions. In order to achieve the required performance and flexibility, the register file supports the following I / O schemes:

♦ output of one 8-bit operand and input of one 8-bit result of calculations;

♦ output two 8-bit operands and enter one 8-bit result of calculations;

♦ output two 8-bit operands and enter one 16-bit result of the calculation;

♦ output one 16-bit operand and enter one 16-bit calculation result.

In fig. 4 shows the structure of 32 general-purpose registers used as microcontroller operating registers.

Fig. 4 - AVR microcontroller general-purpose register file

Most of the instructions that operate the register files have direct access to all of its registers, and most of them are executed in one clock cycle.

As shown in fig. 5, each register also corresponds to an address in the data memory space, where they occupy the first 32 cells. Although registers are not physically included in SRAM, such memory organization provides greater flexibility in accessing registers. A pointer to indirect memory access (one of the X, Y, or Z registers) can be set to any register in the file.

2.3 X-register, Y-register and Z-register

Registers R26-R31, in addition to its main purpose, have an additional function. These registers can serve as 16-bit address pointers for operations using indirect addressing. Three indirect registers of addresses X, Y, and Z are defined as shown in Fig. five.

In various commands that use indirect addressing, these registers can be used as sources of a permanent address, as an address register with automatic address increment, and as a register with automatic address decrement.

Fig. 5 - Dual registers X, Y, Z

Stack pointer

The stack is mainly used:

♦ for temporary storage of data;

♦ to store local variables;

♦ to store the exit address of a subroutine or interrupt handling procedure.

The register of the stack pointer always points to its top.

The stack pointer points to the stack area in the data memory (SRAM). The stack, among other things, is saved;

♦ output address of the subroutine;

♦ the exit address of the interrupt handling procedure.

Therefore, in any program, the address of the beginning of the stack must be determined before any subroutine is called, and before interrupts are enabled. Initially, the stack pointer should be set to an address of at least 0x60.

The stack pointer is decremented by one when data is written to the stack using the PUSH command, and decreases by two when it is written to the return address from a subroutine or interrupt routine.

The stack pointer is incremented by one when the data is read from the stack using the POP command, and incremented by two when data is removed from the stack when the subroutine exits (the RET command) or the interrupt processing routine is completed (the RETI command).

The stack pointer in all AVR chips is executed in the form of two 8-bit I / O registers. The number of actually used bits for each model of microcontrollers is different. In some models, including the ATtiny2313, the data memory is so small that only the youngest of the stack pointer registers (SPL) is used for the stack pointer. The SPH register is missing. The structure of the stack pointer registers for the ATtiny2313 microcontroller is shown below.

Memory ATtiny2313

Now consider the different types of memory microcontroller ATtiny2313. The AVR architecture contains two main types of memory:

♦ data memory;

♦ program memory.

In addition, the ATtiny2313 chip has an EEPROM memory for long-term data storage. All three types of memory are contiguous areas with linearly increasing addresses.

2.4 System flash program memory

The ATtiny2313 chip contains 2 Kbytes of internal reprogrammable memory for storing programs. Since all the commands used in the AVR are 16 or 32 bits in size, the program memory is organized as 1Rx 16. In graphic form, the address space of the program memory is shown in Fig. 6

Fig. 6 - Program Memory Card

Program memory allows at least 10,000 write / erase cycles. The command counter (PC) of the ATtiny2313 chip has 10 binary bits and therefore can work with an address space of 1K. The microcircuit supports the low programming programming memory mode, which can be carried out via a serial SPI interface.

It is also possible to place in the program memory any data that remains unchanged during the program operation. To extract this data from the program memory, use the LPM command.

2.5 SRAM data memory

In fig. 6 shows the organization of the data memory - RAM (SRAM) of the ATtiny 2313 microcontroller. The total address space of the RAM contains 224 cells that are occupied:

♦ file of general purpose registers;

♦ additional I / O registers;

♦ internal data storage.

The first 32 cells are combined with the RON file. The next 64 cells are the standard area where all the I / O registers are located. And only the remaining 128 cells make up the internal data memory.

There are five different ways to address data memory:

♦ straight;

♦ indirect with offset;

♦ indirect;

♦ indirect with predecrement;

♦ indirect with post-increment.

Registers R26-R31 (X, Y, Z) serve as pointers to the address for all operations with indirect addressing.

For direct addressing, the full address of the data byte is indicated.

With indirect addressing with an offset, you can span 63 cells each, starting with the current base address pointed to by the contents of register Y or Z.

When using indirect addressing with automatic pre-decrement and automatic post-decimal, after reading (writing) the memory, the address written in the X, Y or Z register changes.

All 32 general-purpose registers, 64 I / O registers, and 128 bytes of SRAM data memory in the ATtiny2313 chip are available for all memory addressing methods.

EEPROM data memory

ICATtiny2313 contains 128 bytes of EEPROM memory. It is organized as a separate address space for data storage, in which each byte can be separately read or written.

The data exchange between the EEPROM and the central processor is described below and takes place with the help of:

♦ register address EEPROM;

♦ EEPROM data register;

♦ control register EEPROM.

EEPROM reading / writing process

The registers used to access the EEPROM are the usual I / O registers. The availability of the auto-detect time function allows the user program to independently determine the moment when the next byte can be written. If the program contains commands that write to the EEPROM, some precautions must be taken.

In power supply circuits equipped with a good filter, the voltage VCC when switching on and off will vary slowly. This causes the device to operate for some time at a lower voltage than the minimum allowable voltage for a given clock frequency.

3. I / O ports

All ports of AVR microcontrollers in digital input-output mode are full-featured bi-directional ports, in which each of the pins can operate in both input mode and output mode. This means that each individual port bit can be configured either as an input or as an output, regardless of the setting of all other bits of the same port.

You can adjust the port bits using the reset commands and setting the SBI and CBI bits. The same applies to changing the output value (if the discharge is configured as an output) or turning on / off the internal load resistor (if the discharge is configured as an input).

All these settings are made separately for each output port. The output buffer of each of the port pins contains a symmetrical output stage with a high load capacity. The load capacity of each output of any port is sufficient to directly control the LED display.

All pins of any port have individually connected load resistors, which, if necessary, can be connected between this pin and the power source. The input circuits of each port line have two protective diodes connected to the power circuit and to the common wire, as shown in Fig. 7

Fig. 7 - Equivalent circuit of input circuits of one digit of the input-output port

The letter “x” in the register name description means the port name, the waste letter “n” means the number of the digit. When using this name in the program, instead of these symbols, you need to substitute a specific letter of the port name and a specific digit number.

For example, PORTB3 is for bit number 3 of port B, if in the documentation this bit was called PORTxn.

For each input-output port in the microcontroller there are three special registers:

♦ PORTx - data register;

♦ DDRx - control register;

♦ PINx - register of direct reading of the state of the port lines.

The register of direct reading of the state of the lines of the port is read-only, while the data register and the control register are both readable and writeable.

However, it is also possible to write a logical unit to any digit of the PINx register. It will cause the corresponding data register (PORTx) to be switched. Each bit of the PORTx register controls the on and off of the internal load resistor if the corresponding port bit is in input mode.

3.1 Using Ports for Digital I / O

Each port bit is a bi-directional I / O line with the possibility of connecting the internal load resistance. In fig. 8 shows a functional diagram of a single line I / O port. The output contact of this line is indicated in the Pxn diagram.

Fig. 8 - Simplified scheme of one line of digital I / O

Pin configuration

Each port bit is associated with three bits of three special registers: DDxn; PORTxn; PINxn.

As already stated:

♦ DDxn bit is the digit number n of the DDRx register;

♦ The PORTxn bit is the digit number n of the PORTx register;

♦ The PINxn bit is the digit n of the PINx register.

The DDxn bit of the DDRx register selects the direction of information transfer of the corresponding digit. If a logical unit is written to DDxn, the Pxn bit works as an output. If a logical zero is written to DDxn, the Pxn bit acts as an input.

If the port bit is configured as an input, setting the PORTxn bit to one includes an internal load resistor. To disconnect the load resistor you need a logical zero in PORTxn. Immediately after a system reset, all pins of all ports go to the third (high-impedance) state.

If the port bit is configured as an output (setting the PORTxn bit to one), then this unit will appear at the port output. If a logical zero is written to the PORTxn bit, then the output will be zero.

4. External interrupts

4.1 Purpose and Modes of Operation

To call external interrupts, inputs INT0, INT1 or any of the inputs PCINT7-0 are used. If interrupts are enabled, they will be triggered even if the outputs INT0, INT1 and PCINT7-0 are configured as outputs.

This feature provides the ability to generate interrupts programmatically. PCI1 interrupt is an interrupt on a signal change on any of the PCINT7-8 pins. The PCI0 interrupt is an interrupt on changing any PCINT7-0 signal. Moreover, both for interrupting PCI1 and for interrupting PCI0, you can arbitrarily exclude from the operation of any of the inputs assigned to it.

The control registers PCMSK1 and PCMSK0 determine which of the inputs will cause the corresponding interrupt. The change interrupt on pins PCINT7-0 operates asynchronously. Therefore, this type of interrupt can be used to wake up from all sleep modes, except Idle mode.

INT0 and INT1 interrupts support multiple modes. They can be triggered on a leading edge, on a falling edge, or on a static low logic level signal. One of these modes is selected using the external interrupt control register, EICRA.

When one of the INT0 or INT1 interrupts is enabled and configured as a low input interrupt, the interrupt request will be generated as long as there is a low level at the input.

The call of INT0 and INT1 interrupts on a low level is carried out in asynchronous mode. This means that such an interrupt can be used to wake up from any sleep mode except for Idle.

The microcontroller start time is determined using the SUT and CKSEL fuse switches.

5. Eight-bit timer / counter with PWM mode support

5.1 Purpose and Features

The timer / counter T0 is a universal eight-bit counting module with two independent modules of coincidence and with PWM support. It allows you to create specified intervals (for work in real time). It can also serve as a generator of periodic signals.

Consider the main characteristics of the timer / counter.

5.2 Simplified flow chart

A simplified block diagram of an eight-bit timer / counter is shown in Fig. 9. The registers and data transmission circuits available for the central core are shown in bold in the diagram.

Fig. 9 - Block diagram of an 8-bit timer / counter

5.3 Registers

Both the counting timer / counter register (TCNT0) and the both coincidence registers (OCR0A and OCR0B) are eight-bit registers. The presence of an interrupt request (in Figure 10 it is abbreviated as “interrupt call”) can always be determined by the state of the corresponding interrupt flag in the TIFR register.

Each interrupt can be individually masked using the TIMSK timer interrupt mask register. The TIFR and TIMSK registers in fig. 9 not shown.

The timer / counter can be operated from the internal clock generator through a preliminary divider, as well as from an external clock signal fed to the input T0. The clock source selection circuit passes the clock pulses of the selected source to the timer / counter input, and each pulse of this signal increases (or decreases) its value.

If no clock source is selected, the timer / counter stops.

The signal at the output of the clock source selection (clkT0) is called the timer synchronization signal.

The contents of the OCR0A and OCR0B registers are constantly compared with the value of the timer / counter. The result of the comparison can be used by the generator to generate a PWM signal or rectangular variable frequency pulses at one of the OC0A or OC0B outputs.

At the time of a match, the corresponding flag OCF0A or OCF0B is set in one of the channels, which can be used to generate an interrupt request by coincidence.

5.4 Symbols Used

When describing counters, special notation is used for all its important states. These designations are given in table. one.

Designations for basic states of an 8-bit counter

Table 1

5.5 Account Module

The basis of the eight-bit timer / counter is a programmable reversible counter module. In fig. 10 shows a block diagram of a counting module and its control signals.

Fig. 10 - Block diagram of the counting module

Consider the internal signals:

♦ count - increases or decreases the content of TCNT0 by 1;

♦ direction - the choice between decreasing and increasing;

♦ clear - clear TCNT0 (set all bits to zero);

♦ clkT0 - timer / counter clock frequency;

♦ top - occurs when the maximum value is reached by TCNT0;

♦ bottom - occurs when TCNT0 reaches its minimum value (zero).

Depending on the timer mode, each pulse of the clock signal (clkT0) clears, increases or decreases the counter value. The clkT0 signal can be received from both external and internal clock source. This is determined by the clock select bits (CS02: 0). When no clock source is selected (CS02: 0 = 0), the timer stops.

The CPU can access the value of the TCNT0 register regardless of whether the signal clkT0 is present or not. The write command from the central processor takes precedence over all other operations (clearing the counter or counting operations).

Timer modes are determined by setting the WGM01 and WGM00 bits of the TCCR0A register and the WGM02 bit of the TCCR0B register. There is a close relationship between the selected mode of operation of the counter and the frequency of the signal at the OC0A output.

The timer / counter overflow flag (TOV0) is set according to the mode of operation selected with the WGM01 bits: 0. The TOV0 flag can be used to generate CPU interrupts.

5.6 Match Module

The basis of the module is an eight-bit comparator that continuously compares the contents of the TCNT0 register with the contents of each of the two match registers (OCR0A or OCR0B). Each time the TCNT0 content is equal to the OCR0A or OCR0B content, the comparator generates a match signal. This signal sets the corresponding match flag (OCF0A or OCF0B) in the next clock cycle.

If the corresponding interrupt is enabled, setting a match flag causes an interrupt. The match flag is automatically reset when the interrupt handling routine starts. A flag can also be cleared by software by writing a logical unit to it.

In the frequency generator mode, a match signal is used to generate a match output signal and is used to generate a output signal in accordance with the selected mode of operation, which is determined by the WGM02 bits: 0, as well as by the comparison mode selection bits (COM0x 1: 0). The max and bottom signals are used by the frequency generator in some cases to obtain critical values ​​in certain modes of operation. In fig. 11 shows a block diagram of a match module. In the figure, the letter x is a symbol. For different modules, coincidence x is either A or B.

Fig. 11 - Block Diagram of a Match Module

OCR0x registers have double buffering in any pulse width modulation (PWM) mode. In the Normal mode and the JTS mode (Reset on coincidence), double buffering is disabled. Double buffering synchronizes the time of updating the register OCR0x with the moment when the timer reaches the upper or lower limits. Synchronization prevents the occurrence of asymmetric PWM pulses, that is, pulses whose length is equal to an odd number of clock cycles. This ensures high quality PWM signals.

Access to the OCR0x register may seem too complicated. In fact, it is not. If double buffering is enabled, the CPU accesses the OCR0x registers through the buffer. If buffering is disabled, the CPU accesses the OCR0x registers directly.

5.7 Forced change in the exit state of a match

In all non-PWM timer modes, the signal at any of the outputs of the match can be forced to change by writing one to the special bit FOC0x. Forcing a change in the output to match does not set the OCF0x flag, and does not reset the timer.

The signal at the OC0x output will change in the same way as with a real match. That is, the behavior of the OC0x output will depend on the setting of the COM0x1: 0 bits. Depending on the value of these bits, the output signal will either be set to one, or reset to zero, or change its value to the opposite.

5.8. Matching mode lock at the time of writing the register TCNT0

When writing a value to the TCNT0 register, the comparison operation is blocked for one clock input of the timer. This happens even if the timer is stopped. This feature allows you to write to the OCR0x register the same value as the TCNT0 register without causing an interruption when the clock / counter of the clock signal arrives at the input.

5.9 Using the interrupt module

As already mentioned, in any timer mode at the time of recording the register TCNT0, the operation of the comparison module is suspended for one clock period. This can lead to errors when changing the contents of the TCNT0 register, regardless of whether the timer / counter is running or not.

If the value recorded in TCNT0 is equal to the value written in OCR0x, the comparison operation will be skipped, which will cause the timer to work incorrectly in the frequency generator mode.

For the same reason, a value equal to BOTTOM cannot be written to TCNT0 when the meter is in the countdown mode.

The operation of the OC0x output must be configured before the corresponding port line is configured as an output. The easiest way to set the desired value at the OC0x output is to use force setting (the FOC0x bit) in Normal mode. Registers OC0x retain its value when switching modes of signal generation.

5.10 Matching Signal Output Module

Discharges COM0x1: 0 perform two functions. The frequency generator uses the bits COM0x1: 0 in order to determine how the signal at the output of the coincidence module (OC0x) changes at the moment of detecting the fact of coincidence. At the same time, the bits COM0x1: 0 control the signal source at the OC0x output.

In fig. 12 shows a simplified diagram showing the logic of operation of the COM0x1: 0 bits.

Fig. 12 - Output signal coincidence circuit

As can be seen from the figure, the value of COM0x1: 0 affects the state of the input / output port of the chip, regardless of the main control registers of this port (DDR and PORT). And when we talk about the status of OC0x, you need to understand that the internal register OC0x is not the same as the contact of the OC0x chip. Immediately after a system reset, zero is written to the OC0x register.

If any of the bits COM0x1: 0 is set, then the main function of the I / O port is canceled, and the match signal (OC0x) from the frequency generator passes to the output. At the same time, the direction of transmission of the OC0x contact information (input or output) is still dependent on the corresponding bit of the DDR register.

The value of the bit that determines the direction of information transfer for the OC0x output in case it should work as an output must be set before the value of the OC0x register arrives at this output. Alternative port functions are independent of the mode of the signal generator.

5.11 Modes of operation

The mode of operation, that is, the behavior of the timer / counter and the output of the coincidence signal, is determined by the mode of operation of the signal generator (WGM02: 0) and the output mode of the coincidence signal (COM0x1: 0). The state of the bits that determine the output mode of the coincidence signal does not affect the counting sequence, which is determined only by the state of the signal generator configuration bits.

The bits COM0x1: 0 determine whether the PWM output should be inverted or not (inverted or not inverted PWM). For non-PWM modes, the contents of the COM0x1: 0 bits determine whether the output signal should be set to one, reset to zero, or switched to the opposite state at the moment of coincidence.

5.12 “Normal” mode

The “Normal” mode (WGM02: 0 = 0) is the simplest of the timer operation modes. In this mode, the counting direction is always forward (the content increases), and the forced reset of the counter is not performed. The counter simply overflows when it reaches the maximum value for eight digits (TOP = 0xFF), and then restarts from the beginning (0x00).

In normal operation, the timer / counter overflow flag (TOV0) will be set at the moment TCNT0 becomes zero. The TOV0 flag in this case behaves like the ninth bit, and then with the exception that it is only set, but not reset.

Using the timer overflow interrupt, which automatically clears the TOV0 flag, you can increase the program conversion rate by. Normal mode has no special features that would be worth focusing on. The new value of the counting register can be written at any time.

A match module can sometimes be used to trigger interrupts. The use of a coincidence signal for generating signals in Normal mode is not recommended, as this will greatly slow down the processor.

5.13 Reset mode with coincidence (JTS)

In reset mode with coincidence or, alternatively, in the JTS mode (with WGM02: 0 = 2), the OCR0A register is used to control the conversion factor of the counter. In the CTC mode, the counter is reset to zero when the contents of the register counter (TCNT0) and the OCR0A register coincide.

Register OCR0A, thus, determines the maximum value for the counter, and, consequently, its conversion factor.

This mode allows maximum control of the frequency of the signal at the output of the module. The counting of external events is also simplified. The register counter value (TCNT0) is incremented until it coincides between TCNT0 and OCR0A, and then the contents of the counter (TCNT0) are cleared.

An interrupt may be called each time the counter reaches the TOP value. This uses the OCF0A flag. If the interrupt is enabled, the interrupt routine is called, which can be used to update the TOP value.

The TOP setting is too close to the BOTTOM value at the moment when the counter is not working or when the pre-division ratio is low, should be done carefully, since the CTC mode does not have double buffering.

If the new value recorded in OCR0A is lower than the current TCNT0 value, then the source will miss the instant of the match. As a result, the counter will continue counting up to its maximum value (0xFF), then go through zero and only then the coincidence moment will occur.

To generate the output signal in the STS mode, the OC0A output can be set to the output level switching mode each time at the moment of coincidence. To do this, set the bits of the output mode of the coincidence signal (COM0A1: 0 = 1) to the appropriate position. The register value OC0A will not arrive at the corresponding external port contact if it is not configured as an output. The generated signal will have a maximum frequency fOC0 = fclk_I / O / 2, when zero is written to the OCR0A register (0x00). The frequency of the signal can be calculated using the following equation:

where the variable N is the pre-division ratio (1, 8, 64, 256 or 1024).

As in the Normal mode, the TOV0 flag is set every time the counter counts to MAX and goes to zero.

5.14 FastPWM mode (fast PWM)

The microcontroller has several modes of pulse width modulation (PWM). In English, this sounds like Pulse Width Modulation (PWM). Fast PWM (fastPWM) is selected when WGM02: 0 = 3 or 7. In this mode, the highest frequency PWM signal is generated. Fast PWM is different from other PWM modes in that the counter forms only an age sequence for generating a signal. That is, the change in the value of the counter has the form of a sawtooth signal with one-way tilt.

The counting begins with the value BOTTOM and ends with the value TOP. After that, the counter is restarted (the value is set to BOTTOM again). The TOP value is 0xFF with WGM2: 0 = 3.

If WGM2: 0 = 7, the value of TOP is determined by the contents of the OCR0A register. In the non-inverting output mode, the coincidence signal (OC0x) is reset at the moment when the TCNT0 and OCR0x values ​​coincide with the transition to BOTTOM.

In the inverting mode, the output signal is set at the moment of coincidence and transition to BOTTOM. Due to the fact that the counter always works in only one direction, the frequency of the signal in the fast PWM mode can be two times higher than in the phasecorrect mode of the PWM, which uses a two-slope sawtooth signal.

Due to the high frequency of the output signal, the fast PWM mode is well suited for building power control systems, for building rectifiers and D / A converters. High frequency allows you to use external components (coils, capacitors) of small size, and thus reduce the overall cost of the system.

In fast PWM mode, the counter value increases until it reaches the TOP value. In the next cycle of the timer clock, the counter is cleared.

The timer / counter overflow flag (TOV0) is set each time the counter reaches the TOP value. If the interrupt is enabled, the interrupt handling procedure is invoked, which can be used to update the match level.

In fast PWM mode, a coincidence module is used to generate a PWM signal at the OC0x outputs. Setting the bits COM0x1: 0 = 2 will generate a non-inverted PWM signal at the output. To generate an inverted PWM signal, you must set COM0x1: 0 = 3. When setting bits, COM0A1: 0 = 1, the signal at AC0A output at the moment of coincidence switches to the opposite state, provided that the WGM02 bit = 1.

This option is not available for OC0B output. The actual value of OC0x will go to the external contact of the chip only if it is configured as an output.

The PWM signal is generated by setting (reset) the OC0x register at the time of coincidence of OCR0x and TCNT0 values, and resetting (setting) this register in the first clock cycle, after the counter is reset (changing its value from TOP to BOTTOM). The frequency of the PWM signal at the output can be calculated using the following expression:

.

The variable N is a pre-division factor (1, 8, 64, 256, or 1024). Separately, we need to consider several cases when generating a PWM signal, when the value close to the limit value is written to the OCR0A register.

If the OCR0A register is set to a value equal to BOTTOM, then the output signal will be a short burst for each MAX + 1 cycle timer pulse.

If the value of MAX is written to the OCR0A register, then this will result in either a high or a low logic level being permanently present at the output (depending on the value of the bits COM0A1: 0).

The output frequency in the fast PWM mode (at the 50% adjustment level) can be achieved by forcing the OC0x register to switch its logic level with each match (COM0x1: 0 = 1).

The signal thus generated will have the maximum frequency fOC0 = fclk_I / O / 2 in the case when zero is written in the OCR0A register. This feature allows you to switch the OCR0A register in the same way as in the CTC mode, but at the same time use all the advantages of double buffering, which is used in the fast PWM mode.

5.15 PWM phase correct (PhaseCorrectPWM)

Phase correct PWM mode (WGM02: 0 = 1 or 5). The PWM signal is generated with a high conversion factor and a correct phase. Phase correctness is ensured by the counter operating in the sawtooth mode with two-way tilt.

The counter periodically changes the direction of your account. First, he counts from BOTTOM to TOP, then the counting direction changes, and the counter counts TOP to BOTTOM. Then the direction of recalculation changes again, and everything repeats from the beginning.

The TOP value is 0xFF for WGM2: 0 = 1 and is determined by the OCR0A register for WGM2: 0 = 5.

In the non-inverting output mode, the signal at the OCR0x output is reset to zero when the contents of the TCNT0 and OCR0x registers coincide, if the counter is running in the forward direction (for an increase). The value is set to one at the time of coincidence, if the counter is working to reduce.

In the inverted output mode, the picture is reversed. Two-way tilt mode is characterized by a lower maximum frequency of the output signal compared to the previous case where a single-tilt saw is used. Due to the symmetry in phase with bilateral tilt, such modes are preferred when creating motor control systems.

In phase correct PWM mode, the counter value increases until it reaches the TOP value. When the value of the counter reaches TOP, the counting direction changes. The contents of TCNT0 will be TOP for one timer clock period. The timer / counter overflow flag (TOV0) is set each time the counter reaches the BOTTOM value. The interrupt flag can be used to generate an interrupt request. Such an interrupt will be triggered every time the contents of the counter reaches the BOTTOM value.

In phasecorrect mode, the PWM match module is used to generate a PWM signal at the OC0x output. When setting the bits, COM0x1: 0 = 3. Setting the bits. COM0A0 = 1 causes the signal at the OC0A output to be inverted each time at the time of the match, if the WGM02 bit is set. This option is not available for OC0B output. The actual value of OC0x is fed to the external output of the port only if it is configured as an output.

The PWM signal is generated by resetting (setting) OC0x at the time of coincidence of the contents of the OCR0x and TCNT0 registers, when the counter is incremented, and set (reset) at the instant of coincidence, if the counter is decreasing. The frequency of the PWM output signal in phase correct PWM mode can be calculated by the following formula:

,

Where the variable N is the pre-division factor (1, 8, 64, 256, 1024).

The extreme values ​​of the OCR0A register content when generating PWM signals in phase correct PWM mode are special cases. For the non-inverting mode, when writing the BOTTOM value to the OCR0A register, the output will be set to a low logic level. When you write to the OCR0A value MAX, a logical unit will be set at the output. For the inverting mode, the output signal will have opposite values.

6. Description of the command system

6.1 System commands. Command System Overview

In the AVR family, the system of commands for microcontrollers of different types contains from 89 to 130 commands. Microcontrollers of type 2323, 2343, 2313, 4433, 8515 and 8535 have 118 commands in the command system. This command system will be called the base.

In tab. 2.1 - 2.13 describes the operations performed by the commands of the basic system, and mnemonic codes of commands used in the development of the program in AVR Assembly language are given. The tables give a continuous numbering of commands, used later in the text.

The basic command system contains:

▪ 33 commands of register operations, in the performance of which only general-purpose registers are used (commands No. 1-33);

▪ 26 teams addressing the address in the SRAM address space (commands No. 34-59);

▪ 2 commands with reference to input-output registers (commands No. 60 and 61);

▪ 1 team with access to FlashROM (team No. 62);

▪ 22 bit operations commands in bits of general registers and input-output registers (commands No. 63-84);

▪ 34 commands for controlling the course of the program (commands No. 85-118).

The command system of microcontrollers of the t11, t12, t15, 1200, and t28 type, which do not have SRAM, does not include commands with address in the address space of the SRAM except for commands with the LDRd, Z (No. 40) and STZ, Rr (No. 41), which are used to refer to general-purpose registers and input-output registers using indirect addressing. The system of commands for these microcontrollers does not include also 2 commands of register operations (Nos. 32 and 33) and two commands for controlling the course of the program (Nos. 86 and 88). In the case of the 1200 microcontrollers, the command system does not include the command with the FlashROM address, and the m163 type microcontroller, in addition, with the presence of a hardware multiplier.

6 (Rd) -1 → Rd DEC Rd + + + + 7 0 → (Rd) → C LSR Rd + + 0 + + 8 C ← (Rd) ← 0 LSL Rd + + + + + + 9 C → (Rd) → C ROR Rd + + + + + 10 C ← (Rd) ← C ROL Rd + + + + + + 11 Rd.7 → (Rd.6- Rd.0) → C ASR Rd + + + + + 12 Rd.4-7↔ Rd.0-3 SWAP Rd 13 (Rr) → Rd MOV Rd, Rr 14 (Rd) + (Rr) → Rd ADD Rd, Rr + + + + + + 15 (Rd) + (Rr) + C → Rd ADC Rd, Rr + + + + + + 16 (Rd) - (Rr) → Rd SUB Rd, Rr (Yach (Y)) → Rd LD Rd, Y 39 (Rr) → Yach (Y) ST Y, Rr 40 (Yach (Z)) → Rd LD Rd, Z 41 (Rr) → Yach (Z) ST Z, Rr 42 1. (Yach (X)) → Rd2. (X) + 1 → X LD Rd, X + 43 1. (Rr) → Yach (X) 2. (X) + 1 → X ST X +, Rr 44 1. (Yach (Y)) → Rd2. (Y) + 1 → Y LD Rd, Y + 45 1. (Rr) → Yach (Y) 2. (Y) + 1 → Y ST Y +, Rr 46 1. (Yach (Z)) → Rd2. (Z) + 1 → Z LD Rd, Z + 47 1. (Rr) → Yach (Z) 2. (Z) + 1 → Z ST Z +, Rr 48 1. (X) -1 → X 2. (Yach (X)) → Rd LD Rd, -X 49 1. (X) -1 → X 2. (Rr) → Yach (X) ST -X, Rr 50 1. (Y) -1 → Y 2. (Yach (Y)) → Rd LD Rd, -Y 51 1. (Y) -1 → Y 2. (Rr) → Yach (Y) ST -Y, Rr 52 1. (Z) -1 → Z 2. (Yach (Z)) → Rd LD Rd, -Z 53 1. (Z) -1 → Z 2. (Rr) → Yach (Z) ST -Z, Rr 54 (Yach (Y) + q) → Rd LDD Rd, Y + q 55 (Rr) → Yach (Y) + q STDY + q, Rr 56 (Yach (Z) + q) → Rd LDD Rd, Z + q 57 (Rr) → Yach (Z) + q STDZ + q, Rr 58 1. (SP) + 1 → SP 2. (STACK) → Rd Pop rd 59 1. (Rr) -1 → STACK 2. (SP) -1 → SP Push rr d, r = 0-31; q = 0-63 88

(PC) + 1 → STACK

Icall 89

(STACK) → PC

RET 90

(STACK) → PC

RETI k = -2048 - +2047

Table 12

№	Condition	Command mnemonic	№	Condition	Command mnemonic
91	I = 0	BRID k	92	I = 1	BRIE k
93	T = 0	BRTC k	94	T = 1	BRTS k
95	H = 0	BRHC k	96	H = 1	BRHS k
97	S = 02. (X) + 1 → X	BRGE k	98	S = 1	BRLT k
99	V = 0	BRVC	100	V = 1	BRVS k
101	N = 0	BRPL k	102	N = 1	BRMI k
103	Z = 0	BRNE k	104	Z = 1	BREQ k
105	C = 0	BRCC k	106	C = 1	BRCS k
107	C = 0	BRSH k	108	C = 1	BRLO k
109	SREG.b = 0	BRBC b, k	110	SREG.b = 1	BRBS b, k
k = -64 - +63; b = 0 - 7

Table 13

Table 14

№	Operation	Command mnemonic
116	MK → power saving mode	SLEEP
117	WDT restart	WDR
118	Not	NOP

6.3 Register operation commands

The group of register operations includes forwarding, arithmetic and logical operations. Register operation commands are described in Table. 2, 3, and 4 The machine codes of all commands of register operations are in the “word” format, commands No. 1–31 are executed in one clock cycle, and commands No. 32 and 33 are executed in two cycles.

Arithmetic operations — addition and subtraction — can be performed with unsigned numbers in binary code and with signed numbers in an additional binary code. In contrast to microcontrollers of many other families, in which subtraction is reduced to addition with a number with a modified sign (X – Y = X + (-Y)), in microcontrollers of the AVR family, subtraction is performed using a hardware binary subtractor.

When performing arithmetic and logical operations, in addition to the result code, the values ​​of the characteristics of the result are formed. When performing comparison operations (commands No. 18, 19 and 27), only the values ​​of the characteristics of the result are formed.

The values ​​of the result features are represented by the status bits of the SREG Status Register (No. $ 33F). Six result attributes are used, which are named C (SREG.0), Z (SREG.1) N (SREG.2), V (SREG.3, S (SREG.4) and H (SREG.5). 2.1 - 2.3 signs, the values ​​of which are formed when executing commands, are marked with a “+” sign or their name is indicated.

When performing different operations, the value of features is formed according to different rules.

Symptom C takes a single value:

▪ when the transfer unit appears from the high order when performing the operation of addition (commands No. 14, 15 and 32);

▪ when a loan unit appears in the senior level when performing the operation of addition (teams No. 4, 16, 17, 18, 19, 25, 26, 27 and 33);

▪ when the unit leaves the discharge grid when performing a shift operation (commands No. 7, 8, 9, 10 and 11).

A single value of the sign C when performing operations of addition and subtraction with numbers without a sign indicates the receipt of an incorrect result of the operation due to the overflow of the discharge grid.

The sign Z takes a single value when receiving a zero result of the operation. When performing a subtraction operation with a loan (team No. 17, 19 and 26) Z = 1, if zero result is obtained when performing this and previous operations.

The sign N has a value equal to the value of the senior digit of the result code. When performing arithmetic operations with numbers with a sign and no overflow of the discharge grid, it represents the sign of the result.

The sign V takes on a single value if an overflow of the discharge grid occurred during the execution of an arithmetic operation with signed numbers.

  The sign S = NV represents the sign of the result when performing arithmetic operations with numbers with a sign, regardless of the overflow of the discharge grid. When the discharge grid overflows (V = 1), the sign of the result is opposite to the value in the highest digit of the result code.

The sign H takes a single value when there is a transfer unit from the D3 bit to the D4 bit when performing the subtraction operation and when transferring the unit from the D3 bit to the D4 bit when performing a code operation to the left.

6.4 Commands with SRAM address

On commands with access to the address in the SRAM address space, operations are performed to transfer (copy) a byte between the general-purpose register and the element to which the address in the SRAM address space corresponds. Such an element can be a general-purpose register (addresses from $ 00 to $ 1F), an input-output register (addresses from $ 20 to $ 5F), a memory cell in SRAM (addresses from $ 60 to a maximum address in SRAM), a memory cell in ERAM (addresses from the maximum address in SRAM +1 to the maximum address in ERAM).

Commands with addressing in the address space of SRAM are described in Table. 2.4 and 2.5.

The machine codes of commands No. 34 and 35 have the format “2 words”, the machine codes of the remaining commands are the format “word”. Commands are executed in 2 cycles, and when accessing cells in ERAM, in 3 cycles. If necessary, an additional wait can be entered in the command execution cycle when accessing ERAM.

Tables 2.4 and 2.5 use the following new notation:

▪ Cell - general register, I / O register, SRAM memory cell, ERAM memory cell accessed using address A from the SRAM address space;

▪ (YCA) - byte to YCA;

▪X, Y, Z - a pair of general purpose registers X (R26, R27), Y (R28, R29), Z (R30, R31), respectively;

▪ (X), (Y), (Z) - a word in a pair of registers X, Y, Z, respectively;

▪ STACK — YTA, which is accessed using the address stored in the register - the SP stack pointer;

▪ (STACK) - byte in STACK, e;

▪ (SP) - code of the number in the register SP.

In commands No. 34 and 35 direct addressing is implemented. The byte address (A = k) is specified in the command code.

The commands number number 36 - 57 implemented indirect addressing. The byte address is in a pair of registers X, Y, or Z. When executing the commands No. 48 to 53, before the transfer is executed, the address in the pair of registers is hardware decremented by one. When executing the commands No. 54 to 57, the address to which the call is made is equal to the address in the pair of registers Y or Z, incremented by q, which is indicated in the command code. The address in the pair of registers remains unchanged.

In teams Nos. 58 and 59, the code in the stack register is used as the address code. When starting the microcontroller, the code of the number 0 is entered into the register-pointer of the stack. For normal operation of the stack, the code of the other number must be entered into the register-pointer at the beginning of the program. Usually the senior address in SRAM is used as such number. For example, for a type 8515 microcontroller, this address is $ 025F.

6.5 Commands with I / O registers

On commands with reference to the I / O registers, operations are performed to transfer (copy) a byte between the general-purpose register and the I / O register using its number ($ 00 - $ 3F) to select the I / O register. Commands with reference to the I / O registers are described in Table. 6. Machine command codes have the format "word". Commands are executed in one measure.

In tab. 6 uses the following notation:

▪ PrP - I / O register with P number;

▪ (PrP) - byte in the PrP register.

When writing a command mnemonic code, its symbolic name can be used instead of a specific register number. All I / O registers have regular names. Microcontrollers of different types of input-output registers with the same name may have different names. When writing in the mnemonic codes of register names, instead of their number it is necessary to use the version of AVR-Assembler for the microcontroller of this type.

6.6 Team with FlashROM

A command that accesses the FlashROM sends (copies) a byte from half the memory cell in FlashROM to the general register R0. The team is described in table. 2.7. The machine command code has the format "word". The command is executed in three cycles.

Before executing the command, the address corresponding to the memory cell in FlashROM, in which the constant is stored, must be multiplied by 2 and written into a pair of registers Z (nos. $ 30, $ 31).

When multiplied by 2 (shift the code left by one bit), the low-order bit of the ZL register ($ 30) turns out to be 0. When the low-order bit is zero, a byte is selected from the lower half of the FlashROM cell. To select a byte from the top half of the cell, you need a number, the code of which is in the Z pair of registers, to be increased by 1 using the command number 33 with the mnemocode ADIWR30, 1 or ADIWZL, 1.

Writing constants in FlashROM is done while programming the microcontroller.

6.7 Bit operations commands

Commands operations with bits are described in Table. 2.8 and 2.9. Machine codes of all commands have the format "word". Commands Nos. 65 and 66 are executed in 2 cycles, the rest of the teams in 1 cycle.

In tab. 2.8 the following new designation is used:

▪ PrP.b - bit b (b = 0 - 7) of the I / O register with the P number (P = $ 00 - $ 1F (!)), Bit in the PrP.b bit.

The commands No. 63 and 64 are used to transfer (copy) the bit between the specified bit of the general-purpose register and the SREG T-register bit.

Commands Nos. 65 and 66 are set to the required state (0 or 1, respectively) the specified bit of the I / O register, and commands Nos. 67 and 68 - the specified bit of the SREG register.

When recording the mnemonic of the commands Nos. 65 and 66, instead of the register number (P), its symbolic name may be indicated, and instead of the number the digits (b) are the symbolic name of the digit. In the AVR microcontroller family, the bits of many I / O registers have regular names. These names are given in the text when considering the devices in which these bits are used.

In microcontrollers of some types, the bits of like registers with the same name have different numbers. When using regular names of input-output registers in regular names of digits in them, it is necessary to use the AVR Assembler version for the microcontroller of the corresponding type.

When assigning a regular discharge name, it was assumed that this discharge belongs to a specific I / O register, but in the mnemonic of the commands No. 65 and 66, it is necessary to specify both the name / number of the register and the name of the discharge.

The required bit value (0 or 1) in the bits of the input-output registers with numbers from $ 20 to $ 3F is set using the commands of register operations with CBR (No. 29) and SBR (No. 31) instructions, respectively.

In tab. 10 shows the mnemonic codes of commands, by which the bits of the SREG register are set to a certain state (0 or 1) without specifying the digit number in the mnemonic command.

6.8 Program Management Commands

The program control commands group includes unconditional and conditional jumps, switching to energy saving mode, restarting the watchdog timer and the idle command.

In tab. 11 describes the commands of unconditional jump (№№ 85 and 86), unconditional jump with return (№ № 87 and 88), return from the subroutine (№89) and return from the interrupting program (№90). The following new notation is used in the table:

▪ PC - command counter;

▪ (PC) - number code in the program counter;

▪ k - increment the number in the program counter.

When writing a program in assembly language, in the mnemonics of the commands Nos. 85 and 87, instead of the increment k, the label (symbolic address) is written, written before the mnemonic of the command to be executed. The increment is calculated and placed in the machine instruction code in the assembly process.

Machine command codes described in Table. 11, have the format "word". Unconditional jump commands (Nos. 85 and 86) are executed in 2 cycles, unconditional jump and return commands (Nos. 87 and 88) are executed in 3 cycles, and return commands (Nos. 89 and 90) in 4 cycles.

The group of conditional transition teams is divided into two groups. In the commands of the first subgroup, the condition is equal to zero or equal to one of one of the bits in the SREG register. Conditions and mnemonic codes of the first subgroup are given in table. 12. If the condition is fulfilled, a transition is made to the address that is formed using the increment k specified in the command code ((PC) + 1 + k → PC; -64 ≤k≤ 63).

If the condition is not met, the transition to the next command in the program ((PC) + 1 → PC) occurs.

When writing a program in assembly language, instead of incrementing k, a label (symbolic address) is written in front of the instruction mnemonic, which you need to go to if the condition is met.

The machine codes of the commands of the first subgroup have the format “word”. When the condition is met, the command is executed in 2 cycles, if the condition is met - in 1 cycle.

If the condition is not met, a transition is made to the next command in the program ((PC) + 1 → PC). If the condition is satisfied, a transition occurs to the execution of the command following the next ((PC) + 1 + 1/2 → PC). The increment of the number in the program counter (1 or 2) is determined by the format of the machine code of the next command (1 word or 2 words, respectively).

The machine codes of the conditional branch commands of the second subgroup have the format “word”. Commands are executed in one cycle, if the condition is not met, in 2 cycles, if the condition is fulfilled and the next command (K1) has the format “word”, or in 3 cycles, if the condition is not met and the next command (K1) has the format “2 words ".

Bibliography

1. Belov A.V. Tutorial device developer on AVR microcontrollers. - St. Petersburg, "Science and Technology" 2010

2. http://www.atmel.ru/

3. ATtiny 2313 Data Sheet.

4. Grebnev V.V. Microcontrollers of the AVR family of Atmel. –M. "IP Radiosoft" 2002

Atmel is well-known in the global and Russian markets as a manufacturer of a wide range of microcircuits containing non-volatile memory on a chip. For example, ATF16V8 / 20V8 / 22V10 and AFT15xx series programmable logic chips contain EEPROM configuration ROM, AT89C microcontrollers have Flash ROM programs, and AVR microcontrollers use both Flash and EEPROM on the same chip. In the Atmel chip list, for example, there is a two-bank flash memory that supports packet mode, as well as “layered” chips, where in a single package, but on different “layers”, there are crystals of a parallel ROM, a serial ROM and RAM. This article, which does not pretend to be exhaustive, is devoted to Atmel's ROM chips in “pure form”.

Atmel is an innovator in the production of non-volatile memory chips: it was the first to release Flash memory chips with a programming voltage of 5 V in 1989; the first in the world began to produce flash-memory at 3.3, 2.7 and 2.5 V; in 1997, Atmel was the first to offer flash memory with a serial interface. And the list goes on ...

The non-volatile memory chips currently produced by Atmel have a capacity range from 1 Kbps to 256 Mbps. In the near future, the production of 1-Mbps chips will begin. In the product range, there are chips with 8- and 16-bit parallel interfaces, as well as chips with two- and three-wire serial interfaces.

Parallel ICs

Earlier than others, AT27 series chips with an 8-bit interface were released, which in fact were analogous to ROM chips with UV erasure, but Atmel crystals were packed in plastic cases, which significantly reduced the cost of chips. The price of “cheapness” is the impossibility of reprogramming. When it became urgent to update the contents of the memory chip in the system, for example, to upgrade the version, Atmel proposed three series of parallel-chip ROMs with electrical erasure.

The AT28 series, based on the EEPROM technology, has the function of independent rewriting of each byte, which leads to an increase in the chip area and, accordingly, the price of the chip. In the AT29 and AT49 series, built on the basis of the Falsh-technology, a different approach is implemented - it is possible to rewrite the blocks, called sectors. The sector size of AT29 memory chips is smaller than that of other manufacturers, which increases the flexibility of use. The AT49 series contains several sectors of relatively large size and, as a result, has a smaller crystal area and the lowest specific cost. Unlike AT28 series microcircuits, when you need to supply 12 V to erase it, the more modern AT29 and AT49 do not require an additional voltage source for erasing and reprogramming. A convenient technological solution is to organize a boot block in the memory array with separate commands to protect it from erasing. In this area of ​​memory is usually placed program loader, which may also include a utility that performs the function of programming the main ROM array, for example from the serial port. Such a construction of the system allows modification of the contents of the Flash ROM without the use of an external programmer. The second advantage is that small-sized microcircuits can be used in TSSOP enclosures and that there are no ROM panels.

The chips of the above families are available for three supply voltages: standard five-volt chips, chips for operation at a supply voltage of 3.3 V (marked with letters LV) and 2.7 V (marked with letters BV).

The main parameters of typical ROM chips AT49BV are given in Table. one.

Table 1

* N or T - boot block at the lower or upper addresses.

Chips with a parallel interface are mainly used for storing a microprocessor program, which runs directly from the ROM, if the microprocessor's speed is relatively low, or is copied into RAM before starting, which is typical of modern microprocessors. "Parallel" ROM chips can also be used for data storage. For this, even single-chip or erasable ultraviolet radiation chips were used, and with the advent of the first Flash ROM, a breakthrough came for the developers of data collection systems.

However, microcircuits with a parallel interface have disadvantages due to the architecture itself. For write-read operations, it is necessary to work with three buses: addresses, data and control. If the microcontroller uses a multiplexed address-data bus, it is necessary to install additional latch registers on the board to store the address at which memory will be accessed in the next clock cycle. But even if the microcontroller has separate address and data buses, it is necessary to “decompose” all circuits on the printed circuit board. A 1 MB microcircuit requires 20 conductors for an address and 8 conductors for data if a microchip with a byte interface is used, plus control signals, which sometimes takes up a significant area of ​​a printed circuit board, especially if the developed device has increased requirements in terms of overall dimensions.

Another disadvantage is the increased power consumption of the device. It is known that a substantial part of the electric power consumed by the microcircuit is used by its output stages, which should ensure good signal fronts when operating on an external bus having a sufficiently large capacity. A fundamental solution to the problem is to abandon the parallel bus in principle and go to serial data exchange.

Serial ICs

In connection with the general desire to reduce power consumption and miniaturization of electronic devices, the use of memory chips with a serial interface has become topical. The popularity of Atmel's ROM chips is eloquently indicated by the fact that the company has released more than a billion of these chips. Atmel manufactures universal memory chips with I2C, SPI and Microware interfaces, as well as specialized AT17 series configuration memory chips designed for downloading programmable logic chips like FPGA. These chips can be repeatedly reprogrammed in the system. It is noteworthy that AT17 chips can be used not only for downloading Atmel's own ATP FPGAs - AT6000 and AT40K, but also for downloading FPGAs manufactured by Xilinx and Altera. To download the latter, the AT17A family is intended, pin-compatible with Altera's EPC chips. It is worth noting that Atmel is ahead of other firms in the time of the start of mass production of new high-capacity configuration memory chips. In particular, it is the first in the world to produce a low-voltage 2 Mbit IC chip in an 8-pin planar package.

Universal chips of sequential ROMs with a sufficient degree of conditionality can be divided into "slow" and "fast". The first category includes AT24 series chips with an I 2 C interface. This two-wire interface, developed by Philips, is very convenient for exchanging small portions of data at frequencies not exceeding hundreds of kilohertz. A typical example is a home TV or computer monitor with settings memory. AT24 series microcircuits are characterized by a large number of rewriting cycles - up to a million times. Convenient quality is the ability to increase the number of chips on the bus up to 4-8 pieces without adding additional control signals. For this purpose, two or three address outputs are provided on the microcircuits, which are unsoldered accordingly. The nomenclature of AT24 chips is quite wide. Microcircuits are distinguished by the possibility of software protection from recording the entire memory array or its part (half or a quarter of the total capacity of the microcircuit).

The main parameters of typical AT24 series microcircuits are given in Table. 2

table 2

In applications that require a higher data exchange rate, it is optimal to use memory chips with SPI interface developed by Motorola. Atmel chips with SPI interface have a clock frequency from 2 to 50 MHz. It should be clarified that there are two characteristics of the speed of the chips: the above, showing the speed of exchange between the external device and the buffer of the ROM chip, and the speed of the physical copying of the buffer contents into the memory array.

Four signals are used for the exchange with the SPI ROM: clock, input data, output data and the “chip select” signal. This architecture allows you to significantly save space on the printed circuit board, especially when using multiple chips in the device.

Atmel produces two families of ROMs with an SPI interface: the AT25 series, built using EEPROM technology, and the AT45 series, built using Flash technology. In the AT25 series there are representatives based on the Flash technology - these are the AT25F512 / 1024 chips. AT-25 flash chips have a higher exchange rate, but fewer write cycles (10,000 times).

The main parameters of AT25 series chips are given in Table 3.

Table 3

The most interesting is the history of the development of AT45 microcircuits, which is built on the basis of the patented DataFlash ® architecture, which is the property of Atmel. This family has already experienced several generations in its development. The first generation AT45D011 - AT45D161 chips were manufactured using 0.35 μm technology and had a 5 V supply voltage (these chips are no longer being manufactured). Three numbers in the name of the chip mean the following: the first two - the capacity of the chip in megabits, the third - the number of I / O ports. The dimensions of the crystal were quite large, so they were packaged in a SOIC28 package, and most of the conclusions remained unconnected. Thus, on the same place it was possible to install a chip of any capacity. Soon, Atmel mastered the production of low-voltage power supply circuits AT45DB011 - AT45DB321. The latest chip was released in a TSSOP32 package. After switching to 0.25 micron technology, the crystal area has been significantly reduced, and now 1, 2 and 4 Mbit chips are available even in SOIC8 packages.

Although the transition to the SPI interface increased to 20 MHz when switching to 0.25 micron technology, this was not enough for high-capacity microchips. To eliminate the “bottleneck”, microcircuits with a capacity of 64 Mbit and higher were equipped with an additional 8-bit interface. Thus, the AT45DB642 microcircuit can be accessed simultaneously via two ports, with the clock frequency during serial access being 20 MHz, with parallel - 5 MHz.

New DataFlash ® AT45DB1282 and AT45DB2562 chips with a capacity of 128 and 256 Mbps, respectively, are manufactured using 0.18 micron technology. This technology allowed to increase the exchange rate up to 50 MHz over the SPI interface and up to 40 MHz over the byte interface. If the typical cases for AT45 microcircuits of previous generations were considered to be SOIC, then for new high-capacity microcircuits, TSOP chassis became standard.

Chips are available in different sized enclosures (TSOP32, TSOP40 and TSOP48), however they are compatible when mounted on a printed circuit board. If you look at the pinout of the microcircuits in the above cases, you can see that in the TSOP40 case the eight extreme leads (four at each edge) are not used. A similar situation is observed for the TSOP48 package, only the number of free leads here is sixteen. Thus, if the TSOP48 case is diluted on the PCB, you can install a 64, 128 or 256 Mbit chip on this board.

The line of AT45 microcircuits currently manufactured has a range of capacities from 1 Mbps to 256 Mbps. In the process of preparing for industrial production using 0.13 micron technology, there are microcircuits with a capacity of 512 and 1024 Mbit. In addition to the actual memory chips with an SPI interface, Atmel also offers MMC (MultiMediaCard) format modules with a capacity of 2, 4 and 8 MB with a 7-pin connector and a corresponding interface.

Using the SPI interface allows the developer with minimal effort to switch to using higher-capacity chips. As a rule, it’s enough to change two constants in the program for working with SPI ROM - the page size and the number of pages in this chip.

Unlike high-capacity flash memory chips from other manufacturers, Atmel chips do not contain defective bits in the memory array, and there is no need for a quality control procedure for recording data. AT45 chips have a five-volt tolerant I / O, which allows you to directly connect them to a five-volt microcontroller.

The main parameters of AT45 series chips are given in table. four.

Table 4

The article concludes with an example of the AT45 memory function. As the control processor used AVR-microcontroller. The program is written in C language for the compiler company ImageCraft Company. A 30-day demo version of this compiler can be found on the Atmel website at http://atmel.argussoft.ru/soft.htm. File size is 3.9 MB. The at45.h include file is located at http://atmel.argussoft.ru/as-mega.htm.

One of the largest manufacturers of semiconductor electronic circuits is . Microcontrollers, nonvolatile memory modules, complex logic integrated circuits, and semiconductor components for processing mixed signals produced by Atmel can be found in the design of a huge number of electronics and other modern equipment.

Atmel product labeling features

For the whole range of products manufactured by the company, a single standard of marking was developed, which takes into account the variety of technical parameters of a particular group of microcircuits.

All chips manufactured by Atmel are marked as AT XXXXX - X X X X (the X symbol represents alphabetic or numeric characters). If we consider them in order, we get:

• AT - the designation of all chips manufactured by the company;
• XXXXX - designate group, type, manufacturing techniques;
• X - indicates the speed of the device;
• X is a variation of the body of the circuit;
• X is the operating temperature range;
• X - versions.

Group and other parameters are indicated by symbols from the third to the seventh. Their meanings from left to right:

• the group to which the circuit belongs (various types of memory, logic chips, microcontrollers);
• memory types (microprocessors, permanent and sequential memory, programmable and reprogrammable);
• the technology used to make the circuit;

The speed of the circuit can be indicated by two or three digits. For marking the type of case and temperature mode, a large number of symbols are used, the details of which are contained in the manufacturer's documentation.

Consider this labeling example.   : ATMEGA165PV-8AU:

• after the first two letters, which denote the manufacturer, the marking of the family to which this microcontroller is referred to - MEGA;
• digits 16 correspond to the amount of flash memory embedded in the chip, expressed in kb;
• the number 5 indicates the controller version;
• letter P - picoPower manufacturing technology, which provides an economical current consumption in the mode up to 100 nA for the Power down mode;
• V - corresponds to the range of operating voltages from 1.8 to 5.5 volts;
• figure 8 indicates the maximum operating frequency of the chip;
• the letter A corresponds to a TQFP package;
• U denotes the operating temperature range of the crystal from -40 ° C to +85 ° C and the need to use lead-free solder when working with the scheme.

"Directory"   - information on various electronic components: transistors, microchips, transformers, capacitors, lEDs   etc. The information contains everything that is necessary for the selection of components and engineering calculations, the parameters, as well as the enclosure base, typical inclusion schemes and recommendations for the use radioelements.

Atmel® DataFlash® memory chips are ideal for use in various technical applications, regardless of what type of data you need to store. Since the DataFlash functions like a consistently large-capacity EEPROM (Electrically Erasable Programmable Read-Only Memory), it can be used in many technical applications instead, which can significantly reduce the price of the finished product. This article will discuss the AT45DBxx1D series chips.

general description

AT45DBxx1D Series ICs are ideal for use in a variety of technical applications where you need to store digitized data, voice, image, or program code itself. All AT45DBxx1D series memory chips support the RapidS ™ serial interface required for applications requiring device operation at high data transfer rates. RapidS ™ is compatible with SPI (Serial Peripheral Interface - Serial Interface for Peripheral Devices) for clocks up to 66 MHz. The entire memory of each of the representatives of this series is organized as a set of pages of a certain volume. The number of pages and their size are determined depending on the specific model of the chip. In addition to the main memory, microcircuits of this series have one or two additional buffers of static RAM (see Table 1), which allow to obtain data when reprogramming ("flashing") the main memory, as well as recording a continuous data stream. In this case, all reprogramming / erasing operations are self-synchronized. EEPROM operation can be emulated easily using a stand-alone three-step read / modify / write procedure. Unlike conventional Flash memory, which is organized randomly with shared address buses and a parallel interface, DataFlash® chips use the RapidS ™ interface for serial data access. Such a simple data access scheme significantly reduces the number of active pins on the chip, which allows reducing the mass-dimensional parameters of the device in which it is used, as well as increasing its reliability and minimizing switching interferences. Thus, AT45DBxx1D series chips are optimized for use in various commercial and industrial applications that require compactness, low power supply voltage and low power consumption. To simplify the process of “flashing” the AT45DBxx1D series microcircuit, depending on the type, a unipolar power source with a voltage of 2.5 ... 3.6 V (or 2.7 ... 3.6 V) is required. Each chip from the series under consideration is controlled through the CS chip select output (Chip Select), and data is accessed via a 3-wire interface including SI (Serial Input) serial input, Serial Output and clock synchronization (Serial Clock ). The main features and characteristics of AT45DBxx1D series microcircuits are presented in Table. 1. The pinout of the pins and the appearance of the AT45DBxx1D series microcircuits in various packages is shown in fig. one.

Fig. 1. Pinout pinout and appearance of AT45DBxx1D series microcircuits in various packages: a - MLF8, b - SOIC8, c - TSOP28

Table 1. The main features and characteristics of AT45DBxx1D series microcircuits.

Name	Capacity,bit	Up, B	Interface	RAM buffer, byte	Numberconclusions	Type of shell	The sizepages,byte	Numberpages	The sizeblock,kb	The sizesector,kb
						MLF8, TSOP28, SOIC8

Key features of AT45DBxx1D series chips

We list the main features of AT45DBxx1D series flash memory chips:

Power supply from a unipolar source with a voltage of 2.5 ... 3.6 V or 2.7 ... 3.6 V;

RapidS ™ interface (clock frequency up to 66 MHz), compatible with SPI;

User configurable memory page size (see Table 1);

Intelligent programming function;

Flexible data erasure:

• possibility of page-by-page / block-by-block / sector wiping (see Table 1);
• full erasure;

Additional buffers static RAM;

The ability to read a continuous data stream (ideal for applications using shadow RAM);

Low power consumption:

• 7 mA - in active mode;
• 25 μA - in standby mode;
• 5 μA (9 μA for an AT45DB161D type microcircuit) - in standalone mode;

Hardware and software protection functions;

Sector locking to protect program code or stored data;

Private data access with the help of a secret 128-byte register:

• 64-byte user programmable space;
• 64-byte unique identifier of the device;

Compliance with JEDEC standards (Joint Electronic Device Engineering Council - Joint Engineering Council for Electronic Devices);

Data retention period is 20 years;

The minimum number of flashing / erasing cycles per page is 100,000;

Work in the industrial temperature range (-40 ... + 85 ° C);

Environmentally friendly body type.

Table 2 provides a description of the functional purpose of the AT45DBxx1D series ICs.

Table 2. Functional purpose of the AT45DBxx1D series ICs

Designation	Functional purpose	Activelevel	Type ofsignal(entrance/output)
	The choice of crystal.   Setting the active level on this pin allows access to the chip. In the case when there is no active level at this pin, the microcircuit operates in the standby mode and a high resistance is set at the output pin SO. However, it cannot receive data on the input pin SI. Turning on the chip is carried out by changing the signal level from high to low at the CS output, and switching off by changing the level from low to high. At the completion of internal self-synchronizing operations (such as data recording or erasing cycle), the chip enters standby mode only after they are completed
	The clock frequency of the serial interface.   This pin is used to synchronize the operation of the microcircuit and control the flow of data on this interface. The command, address and input data on the SI pin is always synchronized on the rising edge of SCK, while the output on the pin of SO is on the falling edge
	Serial input.   This output is used to input (using sequential shift) all data stored in the chip, including commands and address sequences. The data on the SI pin is always synchronized on the leading edge of SCK.
	Serial output   This pin is used to output (using sequential shift) data stored in the chip. The data on the output SO are always synchronized on the falling edge of SCK
	Write protection When the active signal level is present at this output, all memory sectors marked as protected in the Sector Protection Register will not be available for write or erase operations regardless of whether the Sector Protection Protection command has been issued. or not. WP output functions independently of the software-controlled security method. After the low level on the WP output, the contents of the sector security register cannot be changed. If a write or erase command is sent to the chip while the WP level is set to active, it will ignore the command and return to standby mode (as soon as an inactive level appears on the CS output). In this case, the microcircuit will recognize only commands to enable sector protection and sector blocking (Sector Lockdown). On the output side of the WP, the microcircuit has a high resistance, so if you do not use hardware control of data protection against overwriting / erasing, this output can be left unconnected. It is recommended that WP be connected to VCC
	Reset.   A low level on this pin interrupts the current operation and puts the microchip into standby mode. At the same time, it will be in reset mode as long as there is a low signal on this output. When set to a high level RESET pin, the chip returns to normal operation. The chip has an internal reset circuit (at power-up), so there are no restrictions on the reset during the power-up procedure. If for some reason this pin is not used, it is recommended to keep the signal high on it.
RDY / BUSY (AT45DB161D only, AT45DB321D only)	Ready / Busy.   This output is set to a low level each time the chip executes a self-synchronizing operation (write / erase, compare, transfer data between the buffer and the page). The status "busy" indicates that access to the memory and one of the buffers is closed, while read / write operations from / to other buffers are possible.
	Power supply.   The VCC pin is used to supply power from the source to the microcircuit. It is strongly recommended to use only the voltage set by the manufacturer, otherwise it may lead to failures and memory errors.		A source
	Land. "Earth" in relation to the power source. This pin must be connected to the system ground.

Functional diagram

The general functional diagram of AT45DBxx1D series chips (by the example of AT45DB041D) is shown in fig. 2. The main blocks here are the memory matrix (Flash Memory Array), in which the recorded data is stored, the buffer of the static RAM (Buffer), which allows to receive data when the chip is “flashing”, and also used as an independent address space for reading / writing incoming data and their further transfer to the main memory of the MSP (with subsequent erasure or without it), and an input / output interface (I / O Interface) through which the control and access to the processed data is performed.

Fig. 2. The functional diagram of the chip AT45DB041D

To provide optimally flexible data access, the memory matrix of AT45DBxx1D series chips is divided into three types of segments: sectors, blocks and pages. The number and size of sectors, blocks and pages depends on the specific type of chip (see Table 1). At the same time, work is available in two addressing modes (mode selection by the appropriate command): binary (which addresses a space of a multiple of degree 2) and standard DataFlash® (when more memory is available, which gives additional control over data flow). All software operations are performed at the "page" level, and only the erase operation can be performed on the page, sector, block, or directly above the entire amount of available memory.

Chip operation is controlled by commands from the host machine. Each of the commands is synchronized on the falling edge of the CS pulse and starts with an 8-bit opcode (opcode) followed by the destination address (static RAM buffer or the main memory matrix). When transmitting all the commands of addresses and data, the most significant bit is transmitted first.

In addition to standard read / write / erase operations, the considered family of microcircuits supports software and hardware methods for error protection and incorrect data access. The program method is based on commands from the host machine that enable or disable the protection options, while the hardware one operates on a signal at the WP output. The selection of memory areas to be protected and their current status is determined through the sector protection register and the status register (Status Register).

The limiting and typical electrical characteristics of direct and alternating current chips AT45DBxx1D series are given in Table. 3-5

Table 3. Electrical Limit Characteristics for AT45DBxx1D Series Chips

Table 4. Typical electrical characteristics of the AT45DBxx1D series DC chips

Designation	Parameter	Conditions			Max.	Unitsmeasuring
	Rest current
	Standby current	CS *, RESET *, WP * = V IH, CMOS level on all inputs
	Operating current (data reading mode)	f = 20 MHz; I OUT = 0 mA; V CC = 3.6 V
		f = 33 MHz; I OUT = 0 mA; V CC = 3.6 V
		f = 50 MHz; I OUT = 0 mA; V CC = 3.6 V
		f = 66 MHz; I OUT = 0 mA; V CC = 3.6 V
	Operating current (data write / erase mode)
	Input load current	V IN = CMOS level
	Output leakage current	V I / O = CMOS level
	Low input voltage
	High input voltage
	Low output voltage	IOL = 1.6 mA; VCC = 2.7 V
	High voltage output	IOH = -100 μA

* - low level is active.

Table 5. Typical Electrical Specifications for the AT45DBxx1D Series AC Chip (RapidS ™ / SPI Interface)

Designation	Parameter				Max.	Unitsmeasuring
f SCK	Clock frequency
	Clock frequency for sequential data reading
	Reduced clock frequency for sequential data reading
	Time to transfer page to static RAM buffer
	Time to compare page with static RAM buffer
	Erase and rewrite time	256/264 bytes
		512/528 bytes
	Page rewrite time	256/264 bytes
		512/528 bytes
	Erase page time	256/264 bytes
		512/528 bytes
	Block erase time
	Sector Erase Time
	RESET pulse duration
	Recovery time after reset

Atmel Corporation is a global manufacturer of electronic components.
   Product portfolio - logic chips with a wide optional set, non-volatile memory modules, integrated circuits for processing radio frequency and mixed signals. Today, the company develops and manufactures electronic components used in industry, security systems, computer networks, and automotive.

Atmel was formed in 1984. The company's headquarters is located in San Jose, California, USA. Since August 2006, the President and CEO of the company has been Steven Laub. In total, the corporation employs about 5,100 employees. The founders of the company were Greek brothers George and Gust Perlegos. Their family emigrated to California at a time when Silicon Valley was becoming the center of advanced information technology. After 8 years of experience at Intel, the eldest of the brothers decided to start his own business. He founded his own company and named it by the first letters of the proposed specialization: Advanced Technology MEmory and Logic.

The start-up company was listed only 2 years. Already in 1986, Atmel received a five-millionth contract from General Instrument for the supply of a batch of electronic components.
   In 1989, the company began to produce flash memory, in the early nineties - 1.8V chips.
   In 1995, the AVR microcontroller was launched. Atmel achieved its billionth turnover already in 1996.

In 1998, Atmel bought shares of Telefunken Microelectronic, which allowed the corporation to enter the electronics market for cars and communication devices. In 2000, the production of image sensors and radio frequency information systems using SiGe technology started.

In the history of the company there were not only successes, but also noticeable recessions. So, due to an incorrect definition of market needs, consumers of flash memory with enhanced characteristics were lost. More running were models of low-end manufacturers, Intel and AMD.

Products

Microcontrollers. The Atmel line of microcontrollers includes:

8 and 32-bit AVR microcontrollers. Today, 32-bit microcontrollers are used for those applications where an 8-bit chip is enough. But, since the prices of these elements are virtually the same, developers, using 32-bit devices, can allow a performance margin that is useful for future application upgrades.

Microcontrollers with ARM architecture. The ARM core is based on the ideology of the RISC architecture: a limited set of commands, active use of registers, limited memory access. The 32-bit ARM instruction set includes instructions for accessing the hardware coprocessor, which allows developers to extend the capabilities of the underlying architecture by adding their own coprocessors if necessary.
   - MCU Wireless Atmel microcontrollers, focused on wireless communication using ZigBee® and IPv6 / 6LoWPAN protocols.
- 8051 microcontrollers with functions: 2 UART interfaces, watchdog timer, power failure detection circuit, PCA, SPI and in-circuit debugger, ideal for controlling I / O, power, and motors.

Touch controllers   for the low-power portable device market, which is being manufactured for a new generation of touch panels. The devices use proprietary patented QTouch® capacitive technology.

Non-volatile memory chips. The product line includes chips with various interfaces, architectures and organizations, including paged (Flash) and byte-byte (EPROM) memory access. Especially widely these trace elements are used in applications in which it is necessary to reduce the cost of the final product.

FPSLIC Reconfigurable Systems On Chip. The essence of the technology is in the placement of the AVR core, the FPGA block and the static memory array on a single chip. The main advantages are increased integration, low power consumption, high performance.

Atmel Perspectives

Today Atmel firmly holds the leading position in the world ranking of the production of a wide range of microcontroller devices and memory chips. In 2011, the company announced Xmega microcontrollers with USB interface and LCD controller. They are supposed to be used in industrial automation devices, sports and gaming applications, sophisticated medical equipment, and security systems.

The entire range of Atmel multipurpose microcontrollers is continuously being improved, new crystals are emerging, microchip versions are being updated, software is being expanded to support development.